1. Field of the Invention
The present invention relates generally to a substrate for a semiconductor device, a semiconductor device and a manufacturing method thereof, and more particularly, to a resin encapsulation type semiconductor device reduced substantially to a chip size suitable for high density packaging.
2. Description of the Background Art
Chip-size Package (CSP) semiconductor devices such as QFP (Quad Flat Package) type or BGA (Ball Grid Array) type devices have been in wide use to cope with the recent trend toward lighter and more compact apparatus in the market of electrical appliances and adapt to automated assembly process. Increased speed and number of functions in signal processing by semiconductor elements incorporated in these semiconductor devices require a larger number of external connection terminals.
In such a case, a BGA type device having external connection terminals arranged two-dimensionally at the bottom of the semiconductor device is employed. Some devices are formed to be as small as possible so that they can be incorporated into compact mobile equipment, in other words they are formed to have a size close to the chip size. In one of such BGA type devices, with the surface of a semiconductor chip having MOS transistors or the like formed facing up, connection is made to a wiring (interconnection) board by wire bonding to provide conduction with external connection terminals via a wiring (interconnection) pattern.
A cross section of a conventional resin encapsulation type semiconductor device (Japanese Patent Laying-Open No. 9-121002) is given in FIG. 16.
As shown in FIG. 16, a semiconductor chip 11 is mounted on an insulating substrate 15, and a wiring pattern 16 for connection with semiconductor chip 11 is formed in an outer peripheral region of semiconductor chip 11. Semiconductor chip 11 and wiring pattern 16 are electrically connected by wire bonding using a gold (Au) wire 13. Provided in a region between semiconductor chip 11 and insulating substrate 15 is a land 17 for connection with an external connection terminal which covers the entire opening of a through hole 19 and is electrically connected with wiling pattern 16. Semiconductor chip 11 and Au wire 13 are encapsulated with resin 12, and an external connection terminal 14 is electrically connected to land 17 via through hole 19.
In the semiconductor device having this configuration, through hole 19 of insulating substrate 15 for connecting external connection terminal 14 is formed using dice or a drill, by etching or the like. In the case using dice, if the position, size or number of through holes 19 is changed, dice must be manufactured based on each size, resulting in significant increase in the cost. If a drill is used, the number of steps/cost included in the manufacture of the insulating substrate increases as a function of increase in the number of through holes.
Meanwhile, if through hole 19 is formed by etching, the position, number and size of through holes can be changed simply by changing the mask used for etching the insulating substrate, and therefore such changes can be made less costly. Furthermore, the shape of the through hole can be readily changed.
FIG. 17 is a cross sectional view of insulating substrate 15 having through hole 19 formed by dice or a d(ill, and FIG. 18 is a cross sectional view of insulating substrate 15 having through hole 19 processed by etching. In the case of processing with dice or the like, the wall surface of through hole 19 is formed substantially perpendicular to the forming surface of wiring pattern 16, while in the case of etching, the resulting wall surface of through hole 19 is tapered rather than being perpendicular.
A land shape modified by providing a groove at the wall of a through hole is suggested by the disclosure of a conventional BGA-type semiconductor device (Japanese Patent Laying-Open No. 11-87427), and according to this conventional technique, an escape passage is provided for flux when a solder ball is mounted in order to improve the placing characteristic of the solder ball. Since the land portion does not entirely cover the substrate side of the through hole, the reliability is degraded accordingly.
The above-described semiconductor device is compact and has an area array structure. A semiconductor device having such a configuration is mounted by reflow on a wiring board such as a printed circuit board. After the mounting by reflow, stress is generated at the connection portion between the semiconductor device and the wiring board because of their different line expansion coefficients or the like in a heating cycle or the like. The above-described semiconductor device has one side of the semiconductor chip encapsulated with mold resin, and therefore a bowing part forms in the semiconductor device as shown in FIG. 19 if the temperature changes because of a phenomenon characteristic to a bimetal-like structure of the semiconductor chip and mold resin. The above difference in the line expansion coefficients or the bowing of the semiconductor device could cause cracks at the connection portion between the semiconductor device and wiring board 18, leading to breaking in some cases.
The structure as shown in FIG. 17 in which the wall of the through hole in the insulating substrate is perpendicular to the circuit forming surface is different from the tapered structure as shown in FIG. 18 in the shape of the connection portion between the semiconductor device and the wiring board. The connection portions take shapes conforming to the wall of through hole 19 as shown in FIGS. 20 and 21. If external connection terminal 14 has different shapes as in these figures, the distribution of stress will be different between the connection portions, resulting in different resistance to thermal stress. More specifically, in the structure in FIG. 20, since the stress is dispersed, a high reliability level is secured, while in the case of the tapered structure, the stress concentrates around position A in FIG. 21 and therefore the reliability level is lower in the tapered structure under the same conditions. Hence, changing the shape of the connection portion so as to reduce the concentration of the stress would improve the reliability level.
Since the stress imposed upon the connection portion between the wiring board and the package is generated by difference between the line expansion coefficients of the wiring board and the package and the bowing of the package, the direction of the stress runs radially from the center of the package and the magnitude of the stress increases as a function of the distance from the center of the package.